Memory under test programming and reading device

ABSTRACT

Programming and reading management architecture, particularly for test purposes, for memory devices of the non-volatile type, comprising at least two memory half-matrices, a bidirectional internal bus for the transmission of data to and from the memory half-matrices, a programming unit for each one of the at least two memory half-matrices, and a data sensing unit. The programming units are adapted to program the at least two memory half-matrices and the data sensing unit and the programming units communicate with the bidirectional internal bus to reroute onto the bus reading data and programming data of the at least two memory half-matrices.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a programming and reading managementarchitecture, particularly for test purposes, for memory devices of thenon-volatile type.

2. Discussion of the Related Art

In non-volatile memories it is particularly important to provide anarchitecture that allows quick programming of the memory with presetprogramming voltages.

In conventional architecture, the programming voltage of the variousmemory cells is never uniform due to the drops in voltage along thelines.

The case thus occurs in which the memory cells that are closer to theprogramming means are programmed with an optimum voltage, whereas, asone moves further away from the point where the programming voltage isgenerated, the programming voltage decreases due to the above mentionedvoltage drops of the lines. Therefore, the memory cells which are moredistant from the programming means are programmed with decreasingvoltage values that can differ even considerably from those of thememory cells which are closer to the programming means.

In order to contain the non-uniformity of the programming voltagelevels, it is necessary to program a small number of bits at a time, sothat the voltage value differences are negligible.

This approach is valid when byte programming is performed. It is notequally valid when, during testing, parallel programming is performed toreduce programming time requirements.

Abandoning or containing parallel programming leads to the drawback ofincreasing the programming times at the detriment of the low cost of thefinished memory device.

It is in fact evident that the programming of large memory matrices ishindered by the difficulty in achieving uniform programming voltagesexcept for a small number of memory cells at a time.

This drawback will become increasingly important as memory constructiontechnology improves, leading to ever larger sizes of memories. Theselarger sizes are achieved by reducing the thicknesses and the size ofthe programming lines (this entails higher resistivity).

Furthermore, in the case of the programming of multiple bits inparallel, using a redundancy system for output lines, if there are twodefective cells in two different bit lines, it is not possible to resortto the redundancy lines provided for replacement of the defective lines,since it is not possible to apply redundancy to two different linessimultaneously. This results in the important drawback of having toreject, during testing, a memory device that has this situation, or ofhaving to take a much longer time by using only byte programming.

Regarding the direct memory access function, this function is usuallyprovided by virtue of additional lines that allow direct access to thememory for inspection purposes. The additional lines add to the normallines provided for programming and reading the data, resulting in thedrawback of increasing the space occupation of the memory device and ofreducing its reliability.

SUMMARY OF THE INVENTION

An aim of the present invention is therefore to provide an architecturethat advantageously manages programming, reading, and the various testactivities, particularly for memory devices of the non-volatile type.

Within the scope of this aim, an object of the present invention is toprovide a programming management architecture for memory devices thatperforms programming of the memory matrix with programming voltagecontrol, so as to perform uniform programming for the various memorycells of the matrix.

Another object of the present invention is to provide a programmingmanagement architecture for memory devices, particularly of thenon-volatile type, that performs memory cell programming independent ofthe voltage drops along the programming line.

Another object of the present invention is to provide an architecturefor the programming and reading management, for test purposes, of memorydevices that acquires a reference signal for programming at a point thatis free from voltage drops of any kind.

Another object of the present invention is to provide a programmingmanagement architecture for memory devices, particularly of thenon-volatile type, that performs parallel programming and maintains thepossibility of redundancy of any defective lines.

Another object of the present invention is to provide an architecturefor the programming and reading management of memory devices,particularly of the non-volatile type, for test purposes, that performsdirect memory accesses without requiring additional paths besides thenormal reading paths.

Another object of the present invention is to provide an architecturefor the programming and reading management of memory devices,particularly of the non-volatile type, for test purposes, that providesfor symmetry and reversibility of the reading paths, so as to facilitatepath balancing.

Another object of the present invention is to provide an architecturefor the programming and reading management of memory devices,particularly of the non-volatile type, for test purposes, that minimizesthe size of the memory device.

Another object of the present invention is to provide an architecturefor the programming and reading management of memory devices for testpurposes that preserves substantial independence of the data lines, soas to allow further uses thereof even in a time-shared mode.

Another object of the present invention is to provide an architecturethat is highly reliable, relatively easy to produce and available atcompetitive costs.

This aim, these objects, and others that will become apparenthereinafter are achieved by a programming and reading managementarchitecture, particularly for test purposes, for memory devices of thenon-volatile type, comprising at least two memory half-matrices, abidirectional internal bus for the transmission of data to and from thememory half-matrices, a programming unit for each one of the at leasttwo memory half-matrices, and a data sensing unit. The programming unitsare adapted to program the at least two memory half-matrices and thedata sensing unit and the programming units communicate with thebidirectional internal bus to reroute, onto the bus, reading data andprogramming data of the at least two memory half-matrices.

According to another embodiment of the present invention, a system forreading and programming a non-volatile memory device is disclosed, thesystem comprising a memory matrix divided into a right half-matrix and aleft half-matrix, an internal bus for the transmission of data to andfrom the memory matrix and a number n of data sensing units, eachcomprising a first input coupled to the left half-matrix and a secondinput coupled to said right half-matrix, for respectively reading datafrom the left half-matrix and the right-half matrix, and an outputcoupled to the internal bus. The system further comprises a number 2n ofprogramming units, two of the programming units being associated witheach of the data sensing units, wherein a left one of the twoprogramming units is coupled between the left half-matrix and theinternal bus and a right one of the two programming units is coupledbetween the right half-matrix and the internal bus. The left programmingunits read data from the internal bus and program the data to the lefthalf-matrix and the right programming units read data from the internalbus and program the data to the right half-matrix.

Each data sensing unit comprises a sense amplifier having a first inputcoupled to the left half-matrix and a second input coupled to the righthalf-matrix, a first output and a second output; means for enabling anddisabling the output of the data sensing unit; and output coupling meansfor coupling one of the first and second outputs of the sense amplifierto the enabling and disabling means.

Each programming unit comprises a programming device comprising a firstinput which receives data from the internal bus, a second input whichenables and disables the programming device, a third input for receivinga reference voltage and an output for outputting the data; and directmemory access means for coupling to the memory matrix a direct memoryaccess input from the internal bus.

According to another embodiment of the present invention, an apparatusfor programming and reading data to and from a memory device isdisclosed, the apparatus comprising at least two memory sub-matrices, abidirectional internal bus for the transmission of data to and from thememory sub-matrices, and means for uniformly programming each of aplurality of memory cells coupled to each of a plurality of programminglines of the memory sub-matrices. The uniform programming means programsthe memory cells independent of any voltage drops along the programminglines. The uniform programming means comprises a plurality of datasensing units, each coupled between two of the at least two sub-matricesand a number of programming units, each coupled to a programming line ofone of the at least two memory sub-matrices and to one of the pluralityof data sensing units. Each programming unit comprises a programmingdevice including a first input coupled to the internal bus, a secondinput coupled to receive a reference voltage, a third input coupled toreceive a control signal and an output coupled to the one of the atleast two memory sub-matrices for outputting a programming voltage.

Each programming device further comprises a NAND gate which receives thefirst input and the third input, and outputs the programming voltage toa programming terminal connected to the programming line, and anadjustment device which receives the second input and the programmingvoltage from the programming terminal and outputs an adjustedprogramming voltage to the programming terminal. The adjustment devicecomprises a differential amplifier having an inverting input coupled toreceive the reference voltage from the second input of the programmingunit and a non-inverting input coupled to receive the programmingvoltage from the programming terminal and an output, coupled to transmitthe adjusted programming voltage to the programming terminal.

The apparatus further comprises a direct memory access device fordisabling the output of the programming unit and enabling data from theinternal bus to provide direct access of data from the internal bus tothe programming line, thereby bypassing the programming unit.

BRIEF DESCRIPTION OF THE DRAWINGS

Further characteristics and advantages of the invention will becomeapparent from the description of a preferred, but not exclusive,embodiment of the architecture according to the invention, illustratedonly by way of non-limitative example in the accompanying drawings,wherein:

FIG. 1 is a block diagram of the programming and reading managementarchitecture according to the invention;

FIG. 2 is a more detailed block diagram of a portion of the architectureaccording to the invention shown in FIG. 1;

FIG. 3 is a schematic diagram of the circuitry of a portion of thearchitecture shown in FIG. 2;

FIG. 4 is a more detailed circuit diagram of the circuitry of FIG. 3;

FIG. 5 is a schematic diagram of the circuitry of a portion of thearchitecture shown in FIG. 2;

FIG. 6 is a more detailed circuit diagram of the circuit of FIG. 5; and

FIG. 7 is a schematic diagram of a circuit for generating signalsapplied to the circuit of FIG. 6.

DETAILED DESCRIPTION

With reference to the figures, the architecture according to theinvention involves splitting the memory matrix into at least twohalf-matrices (not shown), a left half-matrix and a right half-matrix.The two half-matrices are arranged so as to face each other. An internalbus, divided into a high bus 1_(H) and a low bus 1_(L), is provided forthe bidirectional transmission of data and auxiliary information to andfrom the memory.

In FIG. 1, the reference numeral 2 designates a programming terminal(which actually represents a number of programming terminals that isequal to the number of word bits of the memory matrix). The referencenumeral 3 designates means for dividing the programming voltage V_(PP),which receive as inputs, both the programming voltage V_(PP) and theprogramming enabling signal PG. The voltage dividing means 3 produce areference voltage VPD-rif.

With reference to the case of splitting the memory matrix into twomemory half-matrices, the architecture according to the inventionprovides for data sensing means, duplicated programming means and directmemory access (DMA) means.

FIG. 1 is directed to a case in which each memory half-matrix is dividedinto a plurality of half-matrix subsections because a hierarchicaldecoding structure is used. Particularly, it is directed to a case inwhich each half-matrix is divided into four half-matrix subsections (notshown). The word size assumed for this exemplifying memory configurationis 16 bits.

According to the invention, for each half-matrix subsection, there aredata sensing means, advantageously constituted by a sense amplifier 4,and duplicated programming means 5_(R) and 5_(L). Each sense amplifier 4is of the reversible symmetrical type and it is therefore possible toswap the matrix branch with the reference branch if the left or rightmemory half-matrix is being read.

FIG. 2 is a detail view of two of the four structures that are providedin each array 10 for each pair of opposite half-matrix subsections,i.e., one that belongs to the left half-matrix and one that belongs tothe right half-matrix.

In particular, FIG. 2 shows that for each array 10 associated with eachhalf-matrix subsection, there are data sensing means 4 and duplicatedprogramming means 5_(R) and 5_(L).

The programming means 5_(R) and 5_(L) are provided in four pairs forevery two opposite half-matrix subsections, since each pair is meant,respectively, for one bit of the left half-matrix subsection and for onebit of the right half-matrix subsection.

Therefore, in summary, for a memory matrix with a 16-bit word length,divided into two half-matrices that are in turn divided into fourhalf-matrix subsections each, there are sixteen sense amplifiers 4 andthirty-two programming means 5 (sixteen for the left half-matrix andsixteen for the right half-matrix). Each array 10 includes four senseamplifiers 4 and eight programming means 5. An additional senseamplifier is provided, for each half-matrix, for the redundancy lines.

In FIG. 1, the reference numeral 10 generally designates a set of foursense amplifiers 4 and of eight programming means 5. FIG. 2 shows two ofthe four sense amplifiers 4 and the two pairs of programming means 5,each pair associated with each sense amplifier 4.

The arrays 10 are connected, by means of the lines YMS-L and YMS-R,respectively to the left half-matrix and to the right half-matrix. Theconnections 11 represent the bidirectional connections to the internalbus 1_(L) and 1_(H). Each array 10 receives in input the referenceprogramming voltage signal VPD-rif, and a bus that carries controlsignals CNT-bus.

With reference again to FIG. 2, only the left portion of said figure,which comprises the sense amplifier 4 and the programming means 5_(R)and 5_(L), is described since the structure and operation of the rightportion is identical to the left portion.

The reference numeral 20 generally designates a data sensing unit andthe reference numeral 30 generally designates a programming unit. Eachdata sensing unit 20 is identical to all other data sensing units 20,and each programming unit 30 is identical to all other programming units30. Sense amplifier 4 receives in input the signals that arrive from thelines YMS-R and YMS-L, which carry the data of the right half-matrix andof the left half-matrix respectively.

The lines YMS-R and YMS-L are bidirectional, since data exchange canoccur from the memory matrix to external lines or, vice versa, the datacan originate externally and reach the memory matrix. The portions ofthe lines that reach from programming units 30 to the sense amplifier 4are unidirectional toward the amplifier 4.

The outputs of the sense amplifiers 4 are the signals SA-R and SA-L,depending on whether the control signal RD-L/R indicates reading of theright half-matrix or of the left half-matrix respectively. The outputsignals SA-R and SA-L of the sense amplifier 4 thus selected are sent toenabling/disabling structures that are generally designated by thereference numeral 6.

Embodiments of enabling/disabling structures 6 are shown in more detailin FIGS. 5 and 6. Structures 6 comprise enabling/disabling means for thepassage of the data of the left half-matrix or of the right half-matrix,designated by the reference numeral 7 in FIGS. 5 and 6, and means 14 forenabling/disabling access of the data of the matrix to the internal bus1, designated by DATA-BUS in FIGS. 5 and 6. The output of theenabling/disabling structures 6 is sent, by means of line 8, to theinternal bus 1_(H) (DATA-BUS).

The programming means 5_(R) and 5_(L) are connected to the internal bus1_(H) by means of the line 8. This connection on line 8 allows externaldata to be programmed to the memory. Likewise, the programming means5_(L) and 5_(R) shown in the right portion of FIG. 2 are connected, bymeans of a similar line 8, to the internal bus, in this case the bus1_(L). The programming means 5_(L) and 5_(R) therefore receive in inputon line 8 (i.e., the connection to the internal bus), the referenceprogramming voltage VPD-rif, and a programming signal PG-R or PG-L thatindicates the half-matrix to be programmed. In the case of theprogramming means 5_(R), the input programming signal is the signal PG-Rfor programming the right half-matrix 5_(R) ; for the programming means5_(L), the input signal is the signal PG-L. The outputs of theprogramming means 5_(L) and 5_(R) are sent respectively on the lineYMS-L and on the line YMS-R for access to the memory half-matrices.

Switching means 12, driven by a direct memory access signal,respectively DMA-R and DMA-L for direct access to the right and lefthalf-matrix, are adapted to interrupt the connection between theprogramming means 5_(R) and 5_(L) and the lines YMS-R and YMS-L and todirectly connect the left and right memory half-matrices to the internalbus 1 (DATA-BUS) by means of the line 8.

FIG. 3 shows the programming unit 30, separated from the architectureaccording to the invention shown in FIG. 2.

FIG. 4 is a detailed schematic of the programming unit 30 shown in FIG.3.

For the sake of generality, the reference numerals are generalized, inthese figures and in the ones that follow, by eliminating the suffixes Land H for the high and low internal buses, respectively.

In detail, the programming unit 30, FIG. 4, comprises logic means 13that receive in input the programming signal PG, the signal L/R thatindicates whether the half-matrix to be programmed is the lefthalf-matrix or the right one, and the line that arrives from theinternal bus 1 for the flow of external data, by means of the bus, tothe memory during programming. The output of the logic means 13 is sentto the programming terminal 22, which is connected to the line YMS-L/Rthat is adapted to connect the outside world to the left and rightmemory half-matrices, respectively.

Means 21 for adjusting the programming voltage receive in input thereference programming voltage VPD-rif produced by the voltage dividingmeans 3 and the programming voltage feedback by the programming terminal22. Adjustment means 21 are advantageously provided, for example, by adifferential amplifier, which receives in input, at its non-invertingterminal, the reference voltage VPD-rif and the output voltage of theprogramming terminal 22 at its inverting terminal.

Switching means 12, advantageously provided by an N-channel transistorwhose gate terminal receives the signal DMA-L/R, allows switching, inthe presence of a direct memory access (DMA-L/R) signal, to the directmemory access function, enabling the direct connection between theinternal bus 1 and the line YMS-L/R that leads to the memoryhalf-matrices.

FIG. 5 shows the data sensing unit 20, separated from the architectureaccording to the invention shown in FIG. 2.

FIG. 6 is a detailed schematic of the data sensing unit 20. This figureexplicitly shows the means 7 for enabling/disabling the flow of data ofthe left half-matrix or of the right half-matrix and the means 14 forenabling/disabling the access of said data to the internal bus 1. Theenabling/disabling means 7 comprise a first structure and a secondstructure of the tristate type, designated by the reference numerals 15and 16 respectively, that receive in input the signals SA-L and LEFT andthe signals SA-R and RIGHT, respectively.

The signals LEFT and RIGHT indicate the side of the memory matrix thatis affected by the reading operation (the left side or the right side,respectively). The output SA-OUT of the enabling/disabling means 7passes through the means 14 for enabling/disabling access to theinternal bus 1, which are advantageously provided by a tristatestructure 17 that receives in input the output signal SA-OUT of theenabling/disabling means 7 and receives, at the gate terminal of itsP-type transistor, a signal HZ for enabling/disabling access to theinternal bus 1. The gate terminal of the N-type transistor of thetristate structure 14 instead receives in input the inverted signal HZ.

FIG. 7 is a view of the circuit for generating the direct memory accesssignals, respectively for the right half-matrix, DMA-R, and for the lefthalf-matrix, DMA-L. The circuit of FIG. 7 comprises a first NOR gate 18,which receives in input the signal LEFT and an inverted direct memoryaccess signal DMAn, and a second NOR gate 19, which receives in inputthe signal RIGHT and the signal DMAn. The outputs respectively of theNOR gates 18 and 19 are the signals DMA-R and DMA-L for direct access tothe right half-matrix and to the left half-matrix respectively.

With reference to the figures, the operation of the architectureaccording to the invention is as follows.

The sense amplifier 4 captures the data of the left half-matrix and ofthe right half-matrix of the memory device. As a consequence of thepresence of signals LEFT and RIGHT that are respectively high and low orvice versa, flow of the data from the left half-matrix or from the righthalf-matrix output from the sense amplifier 4 is enabled by virtue ofthe action of the enabling/disabling means 7 shown in FIG. 6.

When the data have been enabled for flow out from the sense amplifier 4,they are ready to access the internal bus 1 to be sent to the outputterminals (not shown) of the memory device. In this case, the internalbus is used to transfer out the data captured by the reading operation.

This access to the internal bus is controlled by the enabling/disablingmeans 14 according to the enabling/disabling signal HZ. When the signalHZ is high, the enabling/disabling means are in a high-impedancecondition and the data cannot be sent over the internal bus 1.

It should be noted that the redundancy structure also has aconfiguration that is similar to the diagram of FIG. 2, i.e., a datasensing unit 20 and a duplicated programming unit 30.

The use of a sense amplifier of the reversible symmetrical type balancesthe reading paths of the memory matrix and mutually matches thepropagation times for reading the data on one branch or the other of thesense amplifier.

Regarding the programming step, which is timed by the high signal PG(PG-R and PG-L), each one of the two programming units 30 provided forthe left half-matrix and for the right half-matrix is directly connectedto the internal bus 1 for the programming of data present on theinternal bus 1 in the memory half-matrices. In this case, the internalbus carries external data into the memory.

In the case of parallel programming, the signals for programming theleft half-matrix PG-L and for programming the right half-matrix PG-R areboth high to enable simultaneous programming, which occurs on bothhalf-matrices. In this manner, column redundancy efficiency ismaintained, since it is possible to apply redundancy simultaneously totwo defective bit lines in the two memory half-matrices.

In fact, if the bit line that is to be programmed is defective, columnredundancy is performed for the defective line and for the correspondingline in the opposite half-plane simultaneously, allowing the redundancylines provided in replacement of the defective line or lines to beprogrammed simultaneously. In this manner, the memory device is notrejected if two corresponding bits are simultaneously defective, sincethe two corresponding bits always belong to the same bit line, which isnow split into two half-lines that belong to two opposite half-matrices,the left matrix and the right matrix, can be programmed simultaneously.

It should be noted that the redundancy structure also provides for aconfiguration that is similar to the diagram of FIG. 2, i.e., a datasensing unit 20 and a duplicated programming unit 30.

The programming unit 30 includes local adjustment means 21 that areadapted to adjust, by feedback, the programming voltage with which thevarious memory cells of the half-matrices are to be programmed. Thereference voltage VPD-rif is sent to adjustment means 21 together withthe output voltage of the programming terminal 2 provided for the bit tobe programmed. The reference voltage VPD-rif is generated proximate tothe programming terminal 2, so that it is free from the voltage dropsthat are present on the programming line.

The voltage output from the adjustment means 21 and thus fed to theprogramming terminal 2 is adjusted constantly by utilizing the feedback,in adjustment means 21, of the output voltage of the programmingterminal 2. Therefore, the local adjustment means 21 make theprogramming voltage independent of the voltage drops along the lines, soas to ensure uniform programming of the various memory cells.

Adjustment means 21 allow the programming voltage level carried on thelines YMS-L/R to be independent of the number of cells being programmed,without using particular compensation techniques that are common inother approaches.

Direct memory access from the outside of the memory is controlled by theswitching means 12, which are enabled/disabled by the signal DMA-L/R.Direct memory access provides for two dedicated paths 8 that directlyconnect the internal bus 1 to the left and right memory half-matrix,respectively. Generation of the signals DMA-L/R is controlled by thecircuit of FIG. 7, in which the signal DMAn acts as a regulator.

If the direct memory access function is activated (DMAn=0), then ifLEFT=1 and RIGHT=0, i.e., if the involved half-matrix is the left one,then DMA-R=0 and DMA-L=1. If LEFT=0 and RIGHT=1, the opposite situationoccurs.

In practice, it has been observed that the architecture according to theinvention fully achieves the intended aim, since it provides a muchfaster reading and programming path management than conventionalarchitectures. The possibility of simultaneously programming memoryhalf-matrices that belong to different half-planes considerably speedsup the programming step and, at the same time, avoids the need toreject, during testing, a memory device due to the presence of twodefective bits on two different bit lines.

This problem, which is frequent in conventional architecture, was due tothe fact that the programming means that program a memory matrix do notapply redundancy to two different lines simultaneously, whereas this ispossible with the architecture according to the invention. This ispossible because the memory matrix is divided into two half-matrices andthe programming means simultaneously program even multiple bits on onehalf-line of a half-matrix and on the corresponding half-line in theopposite half-matrix. Therefore, it is possible to apply redundancy toboth half-lines and to avoid having to reject the memory device duringtesting or resorting to slower approaches, such as byte propagation.

Programming with a programming voltage that is feedback-adjusted with aconstant reference voltage VPD-rif allows all the memory cells to beprogrammed with a uniform voltage, avoiding the problems of voltagedrops along the lines that, in conventional architecture, caused thelast cells, in terms of programming time order, to be programmed withvoltage values that were distinctly lower than those of the first ones.

Furthermore, the architecture according to the invention ensuresalignment of the voltage VPD-reg with the reference voltage VPD-rif,regardless of the number of memory cells being programmed. Locating thevoltage dividing means 3 proximate to the programming terminal 2 alsomakes the reference voltage VPD-rif immune from any voltage drops. Theprovision of a duplicated programming structure does not increase areaconsumptions, since the area which is already necessarily provided forthe sense amplifiers is used fully for its placement.

Finally, the use of symmetrical and reversible sense amplifiersfacilitates balancing of the reading paths of the memory, with thepossibility of providing uniform data propagation delays on both sidesof the sense amplifiers and uniform data capture. The properties of thearchitecture according to the invention are also maintained for theredundancy portion of the memory device.

The internal bus 1, which is the only path for data transmission intoand out of the memory, provides a minimal and, at the same time,multipurpose transmission structure. In addition to performing thefunction of sending the data outside the memory for reading and, viceversa, of sending the programming data to the memory, this bidirectionaltransmission medium also has the function of transmitting additionalinformation regarding the status of the memory, which can be required,for example, during testing.

The architecture thus conceived is capable of numerous modifications andvariations, all of which are within the scope of the inventive concept.For example, the splitting of the memory matrix into two half-matricesand the division of said half-matrices into four half-matrix subsectionseach are merely examples, since it is possible to perform differentdivisions without abandoning the inventive concept. Furthermore, theenabling/disabling means 14 can also be constituted by two passtransistors, and all the elements disclosed may be replaced with othertechnically equivalent elements.

Having thus described at least one illustrative embodiment of theinvention, various alterations, modifications and improvements willreadily occur to those skilled in the art. Such alterations,modifications and improvements are intended to be within the spirit andscope of the invention. Accordingly, the foregoing description is by wayof example only and is not intended as limiting. The invention islimited only as defined in the following claims and the equivalentsthereto.

What is claimed is:
 1. Programming and reading management architecture,particularly for test purposes, for memory devices of the non-volatiletype, comprising:at least two memory half-matrices; a bidirectionalinternal bus for the transmission of data to and from the memoryhalf-matrices, said bidirectional internal bus extending betweenrespective half-matrices; a programming unit for each one of said atleast two memory half-matrices; and a data sensing unit; saidprogramming units being adapted to program said at least two memoryhalf-matrices by transferring programming data from said bidirectionalinternal bus; and said data sensing unit and said programming unitscommunicating with said bidirectional internal bus to reroute, onto saidbus, reading data and programming data of said at least two memoryhalf-matrices.
 2. Architecture according to claim 1, wherein saidprogramming units are adapted to program said at least two memoryhalf-matrices in parallel.
 3. Architecture according to claim 1, furthercomprising means for direct access to said at least two half-matrices,said means being enabled by a signal for selecting the half-matrix to beaccessed and by a direct access control signal, said direct access meanshaving a duplicated dedicated path for direct access to each one of saidat least two memory half-matrices.
 4. Architecture according to claim 3,wherein said paths for direct access to said memory half-matrices areenabled and disabled by signals that indicate direct access to one orthe other of said memory half-matrices.
 5. Architecture according toclaim 4, wherein said signals that indicate direct access to one or theother of said memory half-matrices are produced by logic means thatreceive a signal for selecting one of said memory half-matrices and aninverted direct memory access signal.
 6. Architecture according to claim1, wherein each one of said programming units is driven by a programmingcontrol signal and by a signal that indicates which of said at least twomemory half-matrices is to be programmed.
 7. Architecture according toclaim 1, wherein each one of said programming units is connected to saidinternal bus and to one of said memory half-matrices.
 8. Architectureaccording to claim 1, wherein said data sensing unit comprises a senseamplifier, means for enabling and disabling a flow of the data of saidat least two half-matrices and means for enabling and disabling accessto said internal bus by the data read from said at least two memoryhalf-matrices.
 9. Architecture according to claim 8, wherein said meansfor enabling and disabling the flow of data comprise tristate structuresthat are driven by signals for selecting said at least two half-matricesto enable and disable the flow of the data related to the selectedhalf-matrix.
 10. Architecture according to claim 8, wherein said meansfor enabling and disabling access of the data of said half-matrices tothe internal bus comprise a tristate structure that is driven by asignal for enabling and disabling access to said internal bus. 11.Architecture according to claim 8, wherein said sense amplifier is of areversible symmetrical type.
 12. Architecture according to claim 1,wherein each one of said at least two memory half-matrices is dividedinto a plurality of half-matrix subsections for the use as hierarchicaldecoding means.
 13. Architecture according to claim 12, wherein each oneof said at least two memory half-matrices is divided into fourhalf-matrix subsections.
 14. Architecture according to claim 13, whereineach one of said half-matrix subsections comprises a data sensing unitand two programming units.
 15. Architecture according to claim 1,further comprising a redundancy line management structure for said atleast two memory half-matrices, said structure comprising a data sensingunit and two programming units, said data sensing unit and saidprogramming units being identical to said data sensing unit and saidprogramming units of normal word lines of said memory half-matrices. 16.Architecture according to claim 15, wherein said data sensing unit andsaid programming units for said redundancy lines communicate with saidinternal bus to reroute, over said internal bus, redundancy data of saidat least two memory half-matrices.
 17. Programming and readingmanagement architecture, particularly for test purposes, for memorydevices of the non-volatile type, comprising:at least two memoryhalf-matrices; a bidirectional internal bus for the transmission of datato and from the memory half-matrices; a programming unit for each one ofsaid at least two memory half-matrices; and a data sensing unit; saidprogramming units having programming lines and being adapted to programsaid at least two memory half-matrices; and said data sensing unit andsaid programming units communicating with said bidirectional internalbus to reroute, onto said bus, reading data and programming data of saidat least two memory half-matrices; wherein each one of said programmingunits comprises means for generating a reference programming voltagethat is adjusted to make the reference programming voltage independentof voltage drops along programming lines.
 18. Architecture according toclaim 17, wherein each one of said programming units comprisesprogramming voltage adjustment means that are adapted to locally adjustthe reference programming voltage so as to make the referenceprogramming voltage independent of voltage drops along programming linesfor programming the memory cells of said at least two memoryhalf-matrices.
 19. Architecture according to claim 18, wherein saidprogramming voltage adjustment means receive in input, said referenceprogramming voltage and said programming voltage generated by saidprogramming terminal.
 20. Architecture according to claim 17, whereinsaid reference programming voltage generation means comprise a voltagedivider that is arranged proximate to said programming terminal. 21.Programming and reading management architecture, particularly for testpurposes, for memory devices of the non-volatile type, comprising:atleast two memory half-matrices; a bidirectional internal bus for thetransmission of data to and from the memory half-matrices; a programmingunit for each one of said at least two memory half-matrices; and a datasensing unit; said programming units being adapted to program said atleast two memory half-matrices; and said data sensing unit and saidprogramming units communicating with said bidirectional internal bus toreroute, onto said bus, reading data and programming data of said atleast two memory half-matrices; wherein said programming units areadapted to program said at least two memory half-matrices in parallel;wherein said programming units adapted to program said at least twomemory half-matrices in parallel are adapted to keep a column redundancyfunction active, said redundancy being performed simultaneously for bothof said at least two memory half-matrices, simultaneously replacingdefective lines of said two half-matrices with redundancy lines.
 22. Asystem for reading and programming a non-volatile memory devicecomprising:a memory matrix divided into a right half-matrix and a lefthalf-matrix; an internal bus for the transmission of data to and fromsaid memory matrix; a number n of data sensing units, each comprising afirst input coupled to said left half-matrix and second input coupled tosaid right half-matrix, for respectively reading data from said lefthalf-matrix and said right-half matrix, and an output coupled to saidinternal bus; and a number 2n of programming units, having programminglines two of said programming units being associated with each of saiddata sensing units, wherein a left one of said two programming units iscoupled between said left half-matrix and said internal bus and a rightone of said two programming units is coupled between said righthalf-matrix and said internal bus; wherein said left programming unitsread data from said internal bus and program said data to said lefthalf-matrix and said right programming units read data from saidinternal bus and program said data to said right half-matrix; whereineach one of said programming units comprises means for generating areference programming voltage that is adjusted to make the referenceprogramming voltage independent of voltage drops along programminglines.
 23. The system of claim 22, wherein each data sensing unitcomprises:a sense amplifier having a first input coupled to said lefthalf-matrix and a second input coupled to said right half-matrix, afirst output and a second output; means for enabling and disabling saidoutput of said data sensing unit; and output coupling means for couplingone of said first and second outputs of said sense amplifier to saidenabling and disabling means.
 24. The system of claim 23, wherein saidsense amplifier is of a reversible symmetrical type.
 25. The system ofclaim 22, wherein said programming units are adapted to program saidleft half-matrix and said right half-matrix in parallel.
 26. The systemof claim 22, wherein each of said left and right half-matrices isdivided into a plurality of half-matrix subsections for use ashierarchical decoding means.
 27. The system of claim 26, wherein each ofsaid left and right half-matrices is divided into four half-matrixsubsections.
 28. The system of claim 27, wherein each of said fourhalf-matrix subsections in each of said half-matrices comprise one datasensing unit and two programming units, one programming unit associatedwith the left half-matrix and the other programming unit associated withthe right half-matrix.
 29. A system for reading and programming anon-volatile memory device comprising:a memory matrix divided into aright half-matrix and a left half-matrix, an internal bus for thetransmission of data to and from said memory matrix, a number n of datasensing units, each comprising a first input coupled to said lefthalf-matrix and second input coupled to said right half-matrix, forrespectively reading data from said left half-matrix and said right-halfmatrix, and an output coupled to said internal bus; and a number 2n ofprogramming units, two of said programming units being associated witheach of said data sensing units, wherein a left one of said twoprogramming units is coupled between said left half-matrix and saidinternal bus and a right one of said two programming units is coupledbetween said right half-matrix and said internal bus, wherein said leftprogramming units read data from said internal bus and program said datato said left half-matrix and said right programming units read data fromsaid internal bus and program said data to said right half-matrix,wherein each data sensing unit comprises, a sense amplifier having afirst input coupled to said left half-matrix and a second input coupledto said right half-matrix, a first output and a second output, means forenabling and disabling said output of said data sensing unit; and outputcoupling means for coupling one of said first and second outputs of saidsense amplifier to said enabling and disabling means, wherein eachprogramming unit comprises: a programming device comprising a firstinput which receives data from said internal bus, a second input whichenables and disables the programming device, a third input for receivinga reference voltage and an output for outputting said data; and directmemory access means for coupling to said memory matrix a direct memoryaccess input from said internal bus.
 30. The system of claim 29, whereinsaid programming device comprises:a gate which receives said first inputand said second input of said programming device and provides an output;a programming terminal which receives said output and outputs aprogramming voltage to said memory matrix; and adjustment means forreceiving said reference voltage from said third input of saidprogramming device and said programming voltage from said programmingterminal and outputting an adjustment voltage to said programmingterminal.
 31. The system of claim 30, wherein said adjustment meanscomprises a differential amplifier having an inverting terminal whichreceives said programming voltage and a non-inverting terminal whichreceives said reference voltage and an output which outputs saidadjustment voltage.
 32. The system of claim 29, wherein said directmemory access means comprises a switch which, in response to a directmemory access signal, switches a connection of said programming unit tosaid memory matrix between said output of said programming device andsaid direct memory access input.
 33. A system, for reading andprogramming a non-volatile memory device comprising:a memory matrixdivided into a right half-matrix and a left half-matrix, an internal busfor the transmission of data to and from said memory matrix, a number nof data sensing units, each comprising a first input coupled to saidleft half-matrix and second input coupled to said right half-matrix, forrespectively reading data from said left half-matrix and said right-halfmatrix, and an output coupled to said internal bus; and a number 2n ofprogramming units, two of said programming units being associated witheach of said data sensing units, wherein a left one of said twoprogramming units is coupled between said left half-matrix and saidinternal bus and a right one of said two programming units is coupledbetween said right half-matrix and said internal bus, wherein said leftprogramming units read data from said internal bus and program said datato said left half-matrix and said right programming units read data fromsaid internal bus and program said data to said right half-matrix,wherein each data sensing unit comprises, a sense amplifier having afirst input coupled to said left half-matrix and a second input coupledto said right half-matrix, a first output and a second output, means forenabling and disabling said output of said data sensing unit; and outputcoupling means for coupling one of said first and second outputs of saidsense amplifier to said enabling and disabling means, wherein saidoutput coupling means comprises a first tristate structure coupled tosaid first output of said sense amplifier and having an output, a secondtristate structure coupled to said second output of said sense amplifierand having an output and means for enabling the output of one of saidfirst and second tristate structures while disabling the output of theother of said first and second tristate structures.
 34. A system, forreading and programming a non-volatile memory device comprising:a memorymatrix divided into a right half-matrix and a left half-matrix; aninternal bus for the transmission of data to and from said memorymatrix; a number n of data sensing units, each comprising a first inputcoupled to said left half-matrix and second input coupled to said righthalf-matrix, for respectively reading data from said left half-matrixand said right-half matrix, and an output coupled to said internal bus;and a number 2n of programming units, two of said programming unitsbeing associated with each of said data sensing units, wherein a leftone of said two programming units is coupled between said lefthalf-matrix and said internal bus and a right one of said twoprogramming units is coupled between said right half-matrix and saidinternal bus; wherein said left programming units read data from saidinternal bus and program said data to said left half-matrix and saidright programming units read data from said internal bus and programsaid data to said right half-matrix; wherein said programming units areadapted to maintain column redundancy, said redundancy being performedsimultaneously for said left half-matrix and said right half-matrix,thereby simultaneously replacing defective lines of said left and righthalf-matrices with redundancy lines.
 35. An apparatus for programmingand reading data to and from a memory device, respectively, theapparatus comprising:at least two memory sub-matrices; a bidirectionalinternal bus for the transmission of data to and from the memorysub-matrices; and means for uniformly programming each of a plurality ofmemory cells coupled to each of a plurality of programming lines of saidmemory sub-matrices, wherein said uniform programming means programssaid memory cells independent of any voltage drops along saidprogramming lines.
 36. The apparatus of claim 35, wherein said uniformprogramming means comprises a plurality of data sensing units, eachcoupled between two of said at least two sub-matrices; anda number ofprogramming units, each coupled to a programming line of one of said atleast two memory sub-matrices and to one of said plurality of datasensing units.
 37. The apparatus of claim 36, wherein each programmingunit comprises a programming device including a first input coupled tosaid internal bus, a second input coupled to receive a referencevoltage, a third input coupled to receive a control signal and an outputcoupled to said one of said at least two memory sub-matrices foroutputting a programming voltage.
 38. The apparatus of claim 37, whereineach programming device further comprises a gate which receives saidfirst input and said third input, and outputs said programming voltageto a programming terminal connected to said programming line, and anadjustment device which receives said second input and said programmingvoltage from said programming terminal and outputs an adjustedprogramming voltage to said programming terminal.
 39. The apparatus ofclaim 38, wherein said gate comprises a NAND gate.
 40. The apparatus ofclaim 38, wherein said adjustment device comprises a differentialamplifier having an inverting input coupled to receive said referencevoltage from said second input of said programming unit and anon-inverting input coupled to receive said programming voltage fromsaid programming terminal and an output, coupled to transmit saidadjusted programming voltage to said programming terminal.
 41. Theapparatus of claim 40, further comprising direct memory access means fordisabling said output of said programming unit and enabling data fromsaid internal bus to provide direct access of data from said internalbus to said programming line, thereby bypassing said programming unit.